Silicon photonic integrated reservoir computing processor with ultra-high tunability for high-speed IM/DD equalization
TL;DR
An SOI-based photonic integrated reservoir-computing processor (PIRCP) with two recurrent nodes and ultra-high tunability — phase, amplitude, delay and detuning all reconfigurable for parameter sweeps. Used to equalise 56 GBaud PAM-4 over 60 km SSMF in the C band: BER below the SD-FEC threshold at 112 Gbps/λ with ROP = −15 dBm, a 5 dBm improvement over non-RC schemes.
Highlights
- SOI photonic integrated reservoir-computing processor (PIRCP) with two recurrent nodes
- Ultra-high tunability across phase, amplitude, delay and detuning frequency
- 56 GBaud PAM-4 over 60 km SSMF (C-band); 112 Gbps/λ at ROP −15 dBm, +5 dBm over non-RC
- Best Student Paper + Cover article at IEEE OGC 2022
Citation
A. Sun, A. Yan, P. Luo, J. Zhang, N. Chi, "Silicon photonic integrated reservoir computing processor with ultra-high tunability for high-speed IM/DD equalization," IEEE OGC 2022, Shenzhen, Dec. 2022.